1. Field of the Invention
The present invention relates to an input/output interface for transmitting/receiving a transmission signal between semiconductor integrated circuits or inside the semiconductor integrated circuit.
2. Description of the Related Art
According to a conventional input/output interface, a transmission signal is transmitted/received by turning a signal line into a high level or a low level corresponding to a binary number. In this case, one-bit data is transmitted by one signal line.
According to the input/output interface like this, the number of the signal lines increases as the bit number of the transmission signal to be transmitted increases. Hence, there are the disadvantages that the chip size of the semiconductor integrated circuit increases or the area of a system board increases as the transmission amount increases. Further, input/output circuits for inputting/outputting data to/from the signal line are necessary for each bit. For this reason, when the number of the signal lines increases, the number of the input/output circuits increases, which causes the disadvantage that charging/discharging currents due to switching increase. Namely, a consumption current increases as a bit width of the data increases. Especially, the data amount handled by portable equipment such as a cellular phone which uses a battery as its power source has been increasing substantially. The increase of the data amount is an important issue because it has a significant influence on the operating time of the portable equipment like the above.
The technology of transmitting the data consisting of the plurality of bits through one signal line is disclosed in Japanese Unexamined Patent Application Publication No. Hei 5-227035 and Japanese Unexamined Patent Application Publication No. Hei 10-107684. In Japanese Unexamined Patent Application Publication No. Hei 5-227035, the logical value is expressed by the pulse width of the pulse signal and the combination of the timings that the transition edges appear. However, the four parameters T1 to T4 are necessary in order to express two-bit data, and hence the structures of the transmitting circuit and the receiving circuit are complicated. Further, since the timing margin is necessary for each of the parameters T1 to T4, the timing design of the transmitting circuit and the receiving circuit is difficult. For this reason, it is necessary to increase the cycle time of the pulse signal.
In Japanese Unexamined Patent Application Publication No. Hei 10-107684, the digital data is expressed by the time difference which is generated by the frame signals being adjacent timewise, in the spread spectrum communication system. In general, this kind of communication system has the complex transmitting/receiving circuits and its power consumption is large.
It is an object of the present invention to provide an input/output interface and a semiconductor integrated circuit which can transmit a large amount of data by a small number of signal lines.
It is another object of the present invention to reduce the number of the signal lines without decreasing a data transfer rate so that the numbers of input circuits and output circuits are reduced and power consumption is reduced.
It is still other object of the present invention to reduce the number of the signal lines without decreasing the data transfer rate so that the wiring area of the signal lines is reduced.
According to one of the aspects of the input/output interface of the present invention, a logical value is expressed by an order that transition edges appear in a plurality of transmission signals transmitting respectively on a plurality of signal lines. For this reason, a large amount of data can be transmitted through the small number of the signal lines according to the combination of the timings that the transition edges appear in the transmission signals. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate.
Since only a small number of the signal lines are necessary, it is possible to reduce the number of the output circuits (output buffers) and the number of the input circuits (input buffers) of the transmission signals. Since the number of the circuits to be operated decreases, power consumption can be reduced on both the transmitting side and the receiving side of the transmission signals. Further, since only a small number of signal lines are necessary, it is possible to reduce the wiring area of the signal lines.
The logic can be expressed by a difference in timings that the transition edges appear (relative value), and hence a standard signal is not necessary. In other words, it is not necessary to synchronize the standard signal between the transmitting side and the receiving side of the transmission signal. Thus, the structures of a transmitting circuit and a receiving circuit of the transmission signal can be simplified.
Moreover, the transmitting circuit for transmitting the transmission signal and the receiving circuit for receiving the transmission signal are formed on separate semiconductor chips, whereby the number of the signal lines to be wired between the semiconductor chips can be reduced. For example, when the semiconductor chips are mounted on a printed-wiring board, the area of the signal lines on the printed-wiring board can be reduced. As a result of this, the size of the printed-wiring board is reduced, which makes it possible to reduce the size of a system and reduce the cost of the system.
The transmitting circuit for transmitting the transmission signal and the receiving circuit for receiving the transmission signal are formed on the same semiconductor chip, whereby the wiring area inside the semiconductor chip can be reduced. As a result of this, the chip size of the semiconductor chip can be reduced and the chip cost can be reduced.
According to another aspect of the input/output interface of the present invention, each of the transmission signals include a plurality of the transition edges, and the logical value is expressed by combining the order that the respective transition edges appear in the transmission signals. Hence, a larger amount of data can be transmitted.
According to another aspect of the input/output interface of the present invention, a logical value is expressed by using the order that the transition edges appear in pulse signals. In this case, only leading edges or trailing edges of the pulse signals, or both of the leading edges and the trailing edges of the pulse signals may be used. When both of the leading edges and the trailing edges of the pulse signals are used, 576 patterns of logic can be expressed by using four signal lines. This exceeds nine-bit binary data (512 patterns). Since the signal lines are structured by three lines or more, the data can be transmitted more efficiently than in the case of transmitting the binary data as it is. Especially, when the present invention is applied to transmission signals with larger bit numbers in general, such as data or addresses, it is possible to reduce the number of bus lines substantially, so that power consumption can be substantially reduced and the size of the device can be reduced.
According to one of the aspects of the semiconductor integrated circuit of the present invention, a transmitting circuit includes, for example, a delay circuit which includes a plurality of delay stages connected in cascade, a selecting circuit and an edge generator. In the delay circuit, the standard signal is received on an initial stage of the delay stages and the standard signal is delayed and outputted as a timing signal from each delay stage. The selecting circuit selects any one of the timing signals for each signal line, according to a logical value. The edge generator generates a transition edge for each transmission signal, in synchronization with each of the selected timing signals. A large amount of data can be transmitted by structuring simple logic circuits like the above.
When the logic is expressed by combining both the leading edges and the trailing edges of the pulse signals, it is suitable to form the delay circuit for outputting the timing signals respectively for the leading edges and the trailing edges, and a first and a second selecting circuits for the leading edges and the trailing edges. For example, an output resistor of an open drain type is formed in the edge generator, whereby a plurality of the transmitting circuits can be connected to the bus line. By forming a decoder for decoding the logical value in the transmitting circuit, the selecting circuit can easily select one of the timing signals according to the result of the decoding by the decoder.
According to another aspect of the semiconductor integrated circuit of the present invention, the receiving circuit includes a comparing circuit including a plurality of comparators and a logical value generating circuit including a decoder. The comparing circuit compares the order that the transition edges appear in the transmission signals. Each comparator is structured by a flip-flop or the like which receives the two different transmission signals. The logical value generating circuit decodes the result of the comparison by the comparing circuit, and generates the logical value based on the result of the decoding. In this case, the receiving circuit may restore the original logical value which is transferred from the transmitting circuit, or it may generate a logical value (for example, inverting logic) which is different from the logical value transferred from the transmitting circuit. Thus, a large amount of data can be transmitted by structuring simple logic circuits like the above.
According to another aspect of the input/output interface of the present invention, a logical value is expressed by a time difference between a transition edge of a transmission signal transmitting on a signal line and the transition edge of a standard timing signal. For this reason, the logical values consisting of a plurality of bits can be transferred by one signal line. Namely, a large amount of data can be transmitted by a small number of the signal lines. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Therefore, it is possible to reduce the number of the signal lines as compared with the conventional art. Since only a small number of the signal lines are necessary, it is possible to reduce the number of the output circuits (output buffers) and the input circuits (input buffers) of the transmission signals. Since the number of the circuits to be operated decreases, power consumption can be reduced on both the transmitting side and the receiving side of the transmission signals. Further, since only a small number of the signal lines are necessary, it is possible to reduce the wiring area of the signal lines.
According to another aspect of the input/output interface and another aspect of the semiconductor integrated circuit of the present invention, the transmitting circuit converts the respective logical values, expressed with a plurality of bits, to predetermined delay time. Each logical value is outputted as the transmission signal, which is behind the standard timing signal by the delay time, where the output is made to the signal line. The receiving circuit detects the time that the transition edge of the transmission signal transmitting through the signal line is delayed, compared to the transition edge of the standard timing signal, and generates the logical value according to the delay time. The transmitting circuit needs to delay the transmission signal by the delay time corresponding to the logical value. The receiving circuit can generate a logical value only by detecting the time that the transmission signal is delayed, compared to the transition edge of the standard timing signal. Therefore, the logical value can be converted to the transmission signal by the simple transmitting circuit and the transmission signal can be converted to a logical value by the simple receiving circuit. The receiving circuit may restore the original logical value which is transferred from the transmitting circuit, or it may generate the logical value (for example, inverting logic) which is different from the logical value transferred from the transmitting circuit. Especially, when the present invention is applied to transmission signals with larger bit numbers in general, such as data or addresses, it is possible to reduce the number of the bus lines substantially, so that the power consumption can be substantially reduced and the size of the device can be reduced.
For example, a variable delay circuit may be formed in the transmitting circuit and a delay time of the variable delay circuit may be changed according to the logical value, thereby generating the transmission signal to be transmitted. Further, the delay circuit for generating the plurality of the timing signals whose phases are different from that of the standard timing signal, and a comparing circuit for comparing the phase of the received transmission signal and the phase of each timing signal and for detecting the delay time of the transmission signal to the standard timing signal may be formed in the receiving circuit, thereby generating the logical value with ease. In this case, a plurality of latch circuits for latching logic levels of the transmission signals by each timing signal are formed in the comparing circuit so that the phase of the transmission signal can be expressed by logic levels to be latched in each latch circuit. Further, a simple encoder is formed in the comparing circuit so that the logical value can be generated based on the logic levels being latched in the latch circuits.
The transmitting circuit and the receiving circuit are formed on separate semiconductor chips, whereby the number of signal lines to be wired between the semiconductor chips can be reduced. For example, when the semiconductor chips are mounted on the printed-wiring board, the area of the signal lines on the printed-wiring board can be reduced. As a result of this, the size of the printed-wiring board is reduced, which makes it possible to reduce the size of the system and reduce the cost of the system.
The transmitting circuit and the receiving circuit are formed on the same semiconductor chip so that the wiring area inside the semiconductor chip can be reduced. As a result of this, the chip size of the semiconductor chip can be reduced, and the chip cost can be reduced.
According to another aspect of the input/output interface of the present invention, since the transmitting circuit and the receiving circuit are respectively formed on a plurality of semiconductor chips, the data can be transmitted/received by a small number of signal lines. In this case, a first input circuit and a second input circuit for receiving a transmission signal and a standard timing signal which is outputted from another semiconductor chip, respectively, are formed for receiving the transmission signal, and a first output circuit for outputting another transmission signal, a signal generating circuit for generating another standard timing signal according to an external clock signal and a second output circuit for outputting the standard timing signal to the exterior of the chip are formed for transmitting the transmission signal, in each semiconductor chip.
In this case, an input of the first input circuit and an output of the first output circuit are connected to a common external terminal and the signal line is allowed to transmit the transmission signal bidirectionally, so that the number of the signal lines can be further reduced. Similarly, an input of the second input circuit and an output of the second output circuit are connected to a common external terminal and the signal line is allowed to transmit the transmission signal bidirectionally, so that the number of the signal lines can be further reduced.